GNSS Time Interval Counter (TIC)

Summary: Development of an FPGA-based Time Interval Counter (TIC) to measure timing differences between a reference 1 PPS signal and a GNSS receiver’s 1 PPS output using coarse-time counting and fine-time measurement techniques.

 

 

Detailed Description:

The GNSS Time Interval Counter (TIC) project focuses on developing an FPGA-based timing measurement system for characterizing the timing performance of GNSS receivers, including GPS and India’s indigenous NavIC system. The system uses the EDGE Artix-7 FPGA development board and AMD Vivado design tools to measure the time difference between a reference Pulse Per Second (1 PPS) signal and the 1 PPS output from a Device Under Test (DUT).

The design incorporates a coarse-time counter driven by a 50 MHz clock, providing a nominal counting interval of 20 ns, alongside the development of a carry-chain-based Time-to-Digital Converter (TDC) for fine-time interpolation within a clock period. The project includes RTL design, simulation, FPGA synthesis and implementation, PPS edge detection, timing analysis, and hardware validation.

The developed system aims to support GNSS receiver timing characterization, PPS synchronization assessment, and laboratory evaluation of precision timing systems. Calibration and experimental validation will be undertaken to establish measurement resolution and accuracy.

 

Status:

• FPGA Platform and RTL Development: In progress
• Coarse-Time Counter Design: In development
• Carry-Chain TDC Integration and Calibration: In progress
• Simulation, Synthesis, and Implementation: Under development and validation
• Hardware Measurement and Accuracy Validation: Pending completion

Technology / Research Area: GNSS, NavIC, FPGA-based timing measurement, Time Interval Counter (TIC), Time-to-Digital Converter (TDC), Artix-7 FPGA, Verilog HDL, Vivado, PPS synchronization, and precision timing.