FPGA-Based Multi-Constellation GNSS Receiver Development

Summary: Development of an FPGA-based GNSS receiver platform for processing satellite navigation signals from multiple constellations and exploring flexible, high-performance positioning and timing solutions.

Detailed Description:

The FPGA-Based Multi-Constellation GNSS Receiver Development project focuses on exploring FPGA technology for implementing flexible and reconfigurable satellite navigation receiver architectures. The project aims to support the processing of signals from multiple Global Navigation Satellite Systems (GNSS), including GPS, GLONASS, Galileo, BeiDou, and India’s indigenous NavIC system, subject to the selected signal bands and receiver architecture.

The proposed receiver architecture encompasses GNSS signal acquisition, tracking, navigation data processing, and the extraction of positioning and timing information. FPGA-based processing offers opportunities for parallel computation, real-time signal processing, and hardware-level optimization. Software-Defined Radio (SDR) platforms and suitable RF front-end hardware can support signal acquisition, algorithm development, and experimental validation.

The project is intended to strengthen indigenous GNSS receiver development capabilities and support research in multi-constellation navigation, receiver performance evaluation, and precision timing applications.

Status: ongoing

Technology / Research Area: GNSS, NavIC, FPGA, SDR, digital signal processing, satellite signal acquisition and tracking, multi-constellation navigation, and receiver architecture development.